This invention generally relates to a method of forming a metal film on a substrate, and specifically relates to a method of manufacturing a field-effect transistor (FET).
Development of a Schottky-junction-type field-effect transistor using a compound semiconductor such as GaAs has been carried out in the art. As is well known, in order to increase the pperating speed thereof, it is essential to reduce the gate length. However, if the gate length is reduced merely by miniaturizing the gate, then the electrical resistance of the gate is increased, thus interrupting the high speed and low noise operation of the field-effect transistor. Therefore, there have been proposed several methods of forming a gate which is T-shaped or mushroom-shaped in section, i.e., a gate whose lower portion in contact with the semiconductor active layer is narrow while whose upper portion is wide; for instance, a method employing a multi-layer resist and a direct-drawing technique with an electron beam, a method using a focused ion beam lithography, and a method using a dummy gate and a planalization technique in combination.
In addition, in order to realize the high speed operation of the field-effect transistor, it is also essential to reduce the source resistance. Therefore, in order to reduce the source resistance, the structure is generally employed in which the active layers of the source/drain regions are deeper and higher in impurity concentration than the active layer under the gate. However, there arises a problem of the positional shift of the active layers (high concentration layers) of the source/drain regions from the gate, as the gate is miniaturized. Recently, as a countermeasure to this, the FET structure has been extensively employed in which the source/drain regions (high concentration regions) and the gate are self-aligned with each other.
An example of a method of manufacturing such a selfaligned FET is a method in which a refractory gate is used; that is, ion implantation of the high concentration layers is carried out with the refractory gate as a mask, and with the gate left as it is, heat treatment is performed to make the ion implanted layers electrically active. Another example is a method in which a dummy gate is first formed, ion implantation of the high concentration layers is carried out with the dummy gate as a mask, the above-described heat treatment is carried out with the dummy gate or the reverse pattern of the dummy gate left on the semiconductor substrate, and thereafter the aimed gate is formed where the dummy gate was.
In forming the above-described T-shaped or mushroom-shaped gate, the method using a multi-layer resist and a direct-drawing technique using an electron beam, or the method using focused ion beam lithography is disadvantageous in that either must use special equipment such as an electron beam or ion beam direct-drawing device. The method using a dummy gate and a planalization technique in combination also suffers from a difficulty that the process is intricate.
The method using a refractory gate in manufacture of the self-aligned FET is still disadvantageous in that, when the gate is miniaturized, the gate resistance is increased, thus interrupting the high speed and low noise operation of the FET. Furthermore, the method using a dummy gate or its reverse pattern is intricate in process.